1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for using the effect of shapes on design-specific attributes to indirectly specify tolerances to be applied in manufacturing semiconductor devices via design intent.
2. Related Art
Traditionally, design data provided to manufacturing to specify the silicon structures comprising an integrated circuit, e.g. in the form of GDSII, contained geometrical information describing a single specific rendering of the silicon layout. Yield was achieved by producing parts very close to the specified geometries. Such a traditional process doesn't account for the fact that most features in any layout are not timing critical, and for such features a certain level of process variation may be tolerable. Less-aggressive optical proximity correction (OPC) for such non-critical features can lower costs. However, traditional manufacturing tools (such as mask synthesis, mask writer, mask inspection, wafer inspection and mask data preparation tools) are not aware of which shapes are critical and which are non-critical.
An article entitled “The New IC Implementation Flow” by Ann Steffora published in the July 2002 edition of EDAVision is incorporated by reference herein in its entirety. This article quotes Graham Bell, director of marketing for Nassda Corp as stating “The RTL to GDSII flow really means that when you are at the RTL stage, you have a sense of what your GDSII is,” On the other hand, with design intent with the RTL to GDSII flow, the whole emphasis is on physical implementation, and that doesn't address the functional verification. “GDSII is not a handoff point anymore. Now we have to worry about manufacturing, OPC effects, implying that blurring that brick wall and it is the RTL to foundry/silicon flow,” Bell concluded.
Another article entitled “Kahng calls for EDA, design, mask shops to talk” by Ron Wilson published Jun. 24, 2003 in Silicon Strategies is also incorporated by reference herein in its entirety. Kahng is described as calling for a “bidirectional design-manufacturing data pipe” to convey data back and forth between chip design teams, mask makers and foundries. This pipe would pass design intent forward to mask makers, so that, for example, they could apply resolution-enhancement technologies only where they would improve post-test yield of dice. In the reverse direction, Kahng's pipe would pass mask and process limitations back to design teams, so they wouldn't for instance insert mask correction features that couldn't be implemented or verified. Kahng provides four examples, which are discussed next.
A first example shares data between process and design teams, so that the impact of area fill and slotting on routing and on electrical parameters could be sharply reduced. In a second example, if the tool that inserted OPC was aware of the actual timing requirements of the nets on which it was working, the amount of OPC features inserted could be dramatically reduced, with a very significant impact on mask cost. This required passing netlist and timing data to the mask shop. In a third example, a small amount of information about the mask writing equipment could greatly enhance the mask data preparation step. In a fourth example, Kahng describes an ideal world, in which analog designers have accurate models of the data preparation, resolution enhancement and lithography processes, so that they could optimize yield. In effect, designers would be working with models of the actual fabricated silicon structures during optimization, rather than with idealized device models. Kahng also said he offered just a small sample of examples from many, if only communication could be established.
Furthermore, an article entitled “A Cost Driven Lithographic Correction Methodology Based on Off the Shelf Sizing Tools” by P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, presented at DAC 2003, Jun. 2-6, 2003, Anaheim, Calif., USA is also incorporated by reference herein in its entirety. This article describes three different levels of OPC (aggressive, medium and none) that can be independently applied to any gate in the design. Synopsys Design Compiler “DC” was used as the synthesis tool. A yield library in which identical cells in the original timing library show up as three “sized” versions with same cell function but different “areas” and “timing” was used as input to the DC. DC was used to perform gate-resizing on a synthesized netlist. This article concludes that it is possible to reduce the cost of OPC while meeting yield and cycle time targets by making OPC aware of slacks and sensitivities in design.
It is well known in the art to transfer a designer's intent in forming certain structures called “dummys” which are commonly used to enhance manufacturability (e.g. to avoid excessive erosion during chemical mechanical polishing as stated in U.S. Pat. No. 6,522,007). Dummys are normally not optical proximity corrected (OPC). Dummys are also not checked during mask inspection (wherein a physical mask generated from geometric data is checked against the electrical design of the circuit). Inadvertent use of dummys in OPC and their use in mask inspection is avoided by placing the dummys on a special layer (also called “reference layer”) in GDSII data.